1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to semiconductor memory devices having bit lines and a method for manufacturing the same.
2. Description of the Related Art
The driving capability of a dynamic random access memory (DRAM) is determined by the capacitance of capacitors. However, as semiconductor devices become highly integrated, the area allocated for forming capacitors within the devices typically becomes reduced and therefore it may be difficult to obtain required capacitance levels. This is because the capacitance of capacitors is directly proportional to the surface area of the capacitor electrodes. Therefore, many efforts have been made to increase the capacitance by increasing the effective surface area.
Along this trend, fabrication technologies have been developed to increase the height of a storage node electrode, to increase the effective surface area thereof. For example, a storage node electrode is formed in a concave or cylindrical shape having a height of more than 1 μm.
However, technology for securing capacitance by increasing the height of a capacitor has its own limit. For example, if the height of the capacitor is increased, it typically leads to an increase in an aspect ratio of the capacitors. Furthermore, it can destroy a capacitor electrode or cause a bridge between adjacent capacitors.
Also, a capacitor over a bit line (COB) structure has been introduced to replace a capacitor under a bit line (CUB) structure to secure a larger capacitor area. More specifically, the CUB has a structure in which a capacitor is formed first, and then bit lines are formed on the capacitor. In the CUB structure, since the bit lines are formed on a capacitor with a relatively large height, short circuits can occur. Accordingly, there is a limit in increasing the height of the capacitors. For this reason, currently available DRAMs have adopted the COB structure having capacitors on the bit lines, which are in turn formed on word lines.
The capacitor in the COB structure includes storage node contact pads, positioned between the bit lines, for connecting a MOS transistor source (or a contact pad connected to the source) to the storage node electrode. If integration of the semiconductor device increases, the distance between the bit lines and the storage node contact pads reduces. This leads to problems where insulation between the bit lines and the storage contact pad is not secured, and any pattern misalignment could cause short circuits between the bit lines and the storage node contact pads.